Summary

Microarchitecture defines how a CPU executes the ISA using concrete structures: fetch, decode, execute, and writeback stages. Pipelines and superscalar issue exploit instruction-level parallelism, while out-of-order cores use renaming, scheduling, and reorder buffers. Caches and the memory hierarchy hide latency; branch prediction curbs control stalls. Hazards data, structural, control are resolved with forwarding, interlocks, and speculation. Throughput vs latency trade offs shape design, as do power and area budgets.